The present invention relates to customizable circuitry, and particularly to customizable circuitry which includes an interconnect for receiving and electrically connecting electrical devices and tape designs for bonding chips to the interconnect. The invention relates to an interconnect which can be produced in gross with an undedicated, universal structure and subsequently customized to a specific application with minimal effort and fabrication, and to a tape design and bonding pad design for bonding chips to the interconnect. Further, the invention also concerns a method for manufacturing the interconnect.
Customizable circuitry, as used herein, refers to that circuitry in which some of the device interconnections are not made during the initial manufacture of the circuitry, but are deferred. This deferral allows the circuitry to be manufactured in large quantities with generic properties, with the specific design details being applied later by the user in a final step called "customization." Integral to customizable circuitry is a generic interconnect structure coupled with a method of bonding the leads of integrated circuit chips to that interconnect structure.
Interconnects, as building blocks for electronic circuitry and microcircuitry, typically receive and support further electrical devices, for example, substrates, i.e., smaller scale interconnects, integrated chips, capacitors, resistors and so forth, which can be electrically connected to one another to provide larger, more complex electrical structures. The interconnects typically have a sandwich-type structure through which a series of wires extend. The wires connect the electrical devices attached to the interconnect according to a plan specified by the interconnect user.
The interconnects are used in a multiplicity of designs, each requiring unique electrical circuitry. Presently, in a majority of the interconnects, the wiring plan is fixed at an early stage of manufacture. In other words, the manufacturer lays down the interconnect wiring according to a specific, predetermined plan. Such interconnects will be referred to as "design specific." As is readily apparent, design specific interconnects cannot be mass produced, except for high volume applications, and are, therefore, time and cost intensive.
There is a need in the interconnect industry for an interconnect design which could be mass-produced in an unspecified manner and thereafter programmed to produce whatever wiring plan is required by the user. Such interconnects will be referred to as "programmable interconnects" and the final step of imposing the wiring plan on the interconnect will be referred to as "customization."
A previous attempt at programmable interconnect design is disclosed in U.S. Pat. No. 4,458,297 to Mosaic Systems, Inc. The Mosaic design provides interconnect wiring in the form of a grid with wires in one direction forming one plane and orthogonal wires forming a second plane. Positioned between the two sets of wires is a layer of amorphous silicon which, though originally non-conductive, can be rendered conductive at specified points of wire overlap. The selective conductivity is achieved through crystallization of the amorphous silicon by applying a voltage differential across the orthogonal wires. The electric field produced by this voltage differential causes the silicon in the region of the overlapped wires to crystallize and become conductive. Therefore, an electrical path is formed between the overlapped wires.
The Mosaic structure is advantageous in that it provides for the mass production of undedicated interconnects which can be customized by the manufacturer or by the end user at a later stage of manufacture. The major disadvantage of the Mosaic technology is that all of the interconnects must be electrically accessible from the edges of the substrate in order to program the discretionary connections. In other words, all of the interconnects extend across the entire length (or width) of the substrate. This limits the possible configurations of the interconnect and severely limits the number of interconnects which a given substrate can accommodate to a small fraction of what could be accomated using a custom interconnect with the same density of wires. Another problem is that this process leaves sections of wire connected to the desired interconnect network which are not needed (except for the programming and test functions) which degrades the performance of the interconnect. Finally, the Mosaic process is additive only. That is, the wire routing is formed by adding electrically conductive segments, i.e., the crystallized silicon bridges. It is very difficult, if not impossible, to undo any connections which have been previously made. Thus, changes to previously programmed substrates, which might be desired to implement design changes, are impractical.
Turning now to the problem of mounting the integrated circuit chips, it is conventional practice to mount such chips on interconnect structures which serve to electrically connect the chips. To achieve efficiency in the resulting customizable circuit, it is important to match the chip bonding technique used to the particular interconnect structure. One technique often used for such mounting is "Tape Automated Bonding" (TAB) in which the integrated circuit chips are mounted on a carrier film or tape.
Accordingly, there exists a need in the art for an improved customizable circuitry including a programmable interconnect which can be mass produced to include an unspecified wiring plan and which can be subsequently specified in the later stages of manufacture or by the end-user with a minimum of effort and time, and which can provide a dense interconnect structure which can be practiced at both the printed circuit and integrated circuit levels, and a bond pad design compatible with such interconnects.